Semiconductor processing builds hundreds of individual IC chips on a wafer. These individual chips are then cut, tested, assembled, and packaged for their various uses. The packaging step in this processing can be an important step in terms of costs and reliability. The individual IC chip must be connected properly to the external circuitry and packaged in a way that is convenient for use in a larger electrical circuit or system.
There are a number of different types of packages for semiconductor device (“semiconductor packages” or “packages”). One type of semiconductor package is called a flip chip in a leaded molded package (FLMP). This package is described in detail in U.S. patent application Ser. Nos. 09/464,885 and 10/413,668, the disclosures of which are incorporated herein by reference. The FLMP contains a leadframe structure that has a die attach pad and leads that extend away from the die attach pad. The die attach pad is coupled to the front side of a semiconductor die with solder. A molding material covers the die attach pad and the front side of the semiconductor die, while the back side of the semiconductor die is exposed through the molding material. The leads extend laterally away from the molding material and are substantially co-planar with the back side of the semiconductor die and a surface of the molding material. The front side of the semiconductor die may contain the gate region and the source region of a MOSFET (metal oxide semiconductor field effect transistor) in the semiconductor die. The back side of the semiconductor die may contain the drain region of the MOSFET. When the semiconductor package is mounted to a circuit substrate, the back side of the die and the leads are connected to conductive lands on the circuit substrate. The circuit substrate may be a printed circuit board.
Such a semiconductor package has a number of advantages. First, because there is a substantially direct electrical connection between the back side of the semiconductor die and the circuit substrate. Because there are short, low-resistance conductive paths between the source and gate regions in the semiconductor die as well as the circuit substrate, the die package resistance is nearly eliminated. This results in one of the industry's lowest RDS(ON) based on the size of the footprint. RDS(ON) is the on-resistance that is associated with turning a MOSFET in the die package on from an off-state.
The second advantage of the above-described semiconductor package is the reduced thickness. For example, compared to a conventional wire bonded SOIC-8 package, which is about 1.6 mm tall, a FLMP can have a height of less than about 1.0 mm. The FLMP can have the same or better electrical and thermal performance while also being smaller than a standard SOIC-8 package. And thinner semiconductor packages are especially desirable as the size of portable electronic devices (such as wireless phones and laptop computers) continue to decrease.
While the above-described semiconductor package has a number of advantages, a number of improvements could be made. When mass producing semiconductor packages of the type described above, a number of problems can occur. The problems include, for example, silicon cracks that form because of an uneven die standoff from the die attach region of the leadframe structure; moisture seepage into the semiconductor package; delamination between the leadframe structure and the molding material; and finally molding material bleed on an exposed die surface and leads (that can hinder the package from functioning efficiently or potentially fail during device applications). Other problems include poor solder adhesion between the circuit board bonding pads and the semiconductor die, as well as uneven cutting during the singulation process.
In one improvement of this method, a Pb-based solder bump has been used to serve as a stress absorber, thereby protecting the silicon die from cracking when a compressive or a thermal stress is applied. See U.S. patent application Ser. No. 10,413,668, the disclosure of which is incorporated herein by reference. However, Pb is an undesirable material to be used in bumps for two reasons. First, it is a hazardous material. Second, the existing electroplated Pb-based solder bumping process is relatively expensive when compared to direct metal bumping processes.